1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same.
2. Description of the Related Art
Flash memories are widely used to store large-volume data in, e.g., cell phones, digital still cameras (DSCs), USB memories, and silicon audio, and the markets of these flash memories keep extending due to the reduction in manufacturing cost per bit (bit cost) resulting from rapid scaling of the device dimension. New applications are also rapidly rising. The result is a favorable cycle in which the rapid scaling-down and the reduction in manufacturing cost find new markets.
In particular, a NAND flash memory has achieved a practical cross-point cell by allowing a plurality of active areas (AAs) to share a gate electrode (GC), and its simple structure allows rapid progress of scaling. NAND flash memories are beginning to be widely used for storage purposes in, e.g., the USB memories and silicon audio described above, since the above-mentioned rapid scaling-down reduces the bit cost. Accordingly, the recent NAND flash memories are leading devices of LSI (Large Scale Integration) scaling, and the minimum half pitch has reached 0.1 μm or less even on the mass-production level. Although the technical difficulties are also abruptly increasing with the rapid scaling of the dimension, demands are arising for further scaling in the future.
Unfortunately, many problems must be solved to further scaling of flash memories. The problems are enumerated below:
(1) The development of lithography techniques cannot follow the rapid device scaling. Presently, mass-production of lithography apparatuses starts immediately after they are put on sale. In the future, therefore, it is necessary to increase the bit density while keeping the lithography techniques in status quo.
(2) Since the dimensions of elements decrease as micropatterning progresses, the short-channel effect or narrow-channel effect abruptly worsens. This makes it difficult to ensure the reliability and increase the operating speed of nonvolatile memories generation by generation.
(3) As scaling advances, the dimensions of elements decrease. Therefore, statistical variations in numbers of atoms of dopant impurities of transistors and the like presumably worsen the device characteristics or the variations in device characteristics in the future.
Accordingly, it is highly likely to become difficult to continuously increase the bit density in the future by simple scaling of elements size in the horizontal plane only.
The present inventor, therefore, has invented a stacked memory as a semiconductor memory structure capable of relatively easily increasing the bit density of memory elements, without entirely depending upon micropatterning of the lithography techniques, and a method of manufacturing the stacked memory.
As well-known examples of stacked memories, methods of sequentially stacking memory layers as described in patent references 1 to 8, and some stacked memories are presently mass-produced. However, any of these methods forms memory layers by stacking one layer at a time. If the number of memory layers increases, therefore, the number of manufacturing steps largely increases.    [Patent reference 1] Jpn. Pat. Appln. KOKAI Publication No. 7-235649    [Patent reference 2] U.S. Pat. No. 6,534,403B2    [Patent reference 3] United States Patent Application Publication Pub. No. US2005/0014334A1    [Patent reference 4] United States Patent Application Publication Pub. No. US2005/0012119A1    [Patent reference 5] United States Patent Application Publication Pub. No. US2005/0012120A1    [Patent reference 6] United States Patent Application Publication Pub. No. US2005/0012154A1    [Patent reference 7] United States Patent Application Publication Pub. No. US2005/0012220A1    [Patent reference 8] United States Patent Application Publication Pub. No. US2005/0014322A1